Voltage converters are known that provide regulated output load voltages at levels above, at, or below nominal input supply voltages at the same or inverted polarity. Diagrams of two such known converters are broadly shown in FIGS. 1A and 1B. FIG. 1A depicts a step-up, or boost, converter that includes an integrated circuit switching regulator such as, for example, the LT1930 produced by Linear Technology. FIG. 1B depicts an inverting converter that includes a switching regulator such as, for example, the LT1931 produced by Linear Technology, or equivalent. In each device, the switching regulator and control circuit therefor are incorporated in an integrated circuit chip 10, which has a plurality of pins formed thereon for interfacing with external elements.
Each converter comprises an input capacitor 12, coupled between voltage supply input node VIN and ground, and an output capacitor 14 coupled between output node VOUT and ground. The output node is coupled to a load to provide regulated voltage thereto. Resistors 16 and 18 are coupled in series between the output node and ground. The junction between resistors 16 and 18 provides a feedback voltage that is proportional to the load voltage.
The conversion functionality is dependent upon the configuration of the external elements and their connections with the pins of chip 10. In the boost converter of FIG. 1A, inductor 20 and diode 22 are coupled in series between the VIN and VOUT nodes. The junction between inductor 20 and diode 22 is coupled to a switch internal to the chip 10 via a pin SW. The feedback voltage is coupled to a switch control circuit internal to the chip 10 via a pin FB. In the inverting converter of FIG. 1B, inductor 20 capacitor 24 and inductor 26 are coupled in series between the VIN and VOUT nodes. Diode 22 is coupled between the junction of capacitor 24 and inductor 26 and ground. Capacitor 28 is coupled in parallel with resistor 16. The feedback voltage is coupled to via a pin NFB.
The integrated circuit chip 10 for both converters comprises similar, well-known, circuitry. FIG. 2 is a partial block diagram that illustrates chip elements to the left of the dashed line area and typical external regulator elements represented by block 15. Signal responsive switch 30 and resistor 32 are connected in series between inductor 20 and ground. The switch current ISW is sensed at the junction between switch 30 and resistor 32. Switch 30 is controlled by circuit 34. When switch 30 is in a conductive state, current flows from source VIN through inductor 20 and resistor 32 to ground. When the switch is turned off, energy stored in the inductor is transferred to the capacitor 14. By appropriately timing the on and off states of the switch 30, a regulated boost voltage is maintained at the output node of capacitor in the configuration of FIG. 1A, or a regulated inverted voltage is maintained at the output node of capacitor in the configuration of FIG. 1B.
Switching control circuit 34 typically comprises latch circuitry and switch driver circuitry. A set input is coupled to clock 36, which may generate pulses in response to an oscillator. During normal operation, the latch is activated to initiate a switched current pulse when the set input receives each clock pulse. The switched current pulse is terminated when the reset input receives an input signal, thereby determining the width of the switched current pulse. The reset input is coupled to the output of comparator 38. For boost regulation, output voltage feedback signal VFB is coupled to a negative input of error amplifier 40. A voltage reference VREF is applied to the positive input of error amplifier 40. Capacitor 42 is coupled between the output of error amplifier 40 and ground.
The level of charge of capacitor 42, and thus its voltage VC, is varied in dependence upon the output of amplifier 40. As load current increases, the output voltage, and thus VFB, decreases. As the feedback voltage VFB decreases, VC increases. Thus, VC is proportional to load current. VC is coupled to the inverting input of comparator 38. The non-inverting input is coupled to adder 44. Adder 44 combines signal ISW, which is proportional to the sensed switch current, with a compensation signal. Upon switch activation in response to a clock set signal, switch current builds through inductor 20. When the level of the signal received from adder 44 exceeds VC, comparator 38 generates a reset signal to terminate the switched current pulse. During heavier loads, VC increases and the switched current pulse accordingly increases in length to appropriately regulate the output voltage VOUT at the boost level. Such operation is typical current mode control. Alternatively, duty cycle can be regulated in voltage mode control.
In the boost configuration of FIG. 2, the output voltage is a positive level and the positive feedback voltage VFB is applied to the FB pin, shown in FIG. 1A. For an inverting converter, the output voltage is a negative level and the negative feedback voltage VFB is applied to the NFB pin, shown in FIG. 1B. The feedback voltage is then changed in sign to a positive value and applied to the negative input of error amplifier 40. Thus the elements, of a single integrated circuit chip, shown in FIG. 2, can be made operable for both boost and inverting regulation.
Traditional methods for implementing a single integrated circuit chip for use in either a boost or inverting voltage converter require the use of two or three pins of the chip. One conventional method is illustrated in FIGS. 3A-3C. FIG. 3A depicts chip 10 with pins A, B and C illustrated. Pin A is permanently connected to voltage reference VREF, supplied by an external source. Pin B is connected internally to the positive input of error amplifier 40. Pin C is connected internally to the negative input of error amplifier 40. Additional connections are made externally to pins A, B and C to provide for the boost regulation configuration, as illustrated in FIG. 3B, or the inverting regulation configuration, as illustrated in FIG. 3C.
In the FIG. 3B arrangement, pins A and B are connected together externally. Thus VREF is applied to the positive input of error amplifier 40. Feedback voltage VFB, from the junction of resistors 16 and 18 is applied to the negative input of error amplifier 40 via pin C. This configuration is the same as that illustrated in FIG. 2. The output of error amplifier 40 will vary in accordance with the output load and the switch 30 is controlled accordingly.
In the FIG. 3C arrangement, pin C is connected externally to ground. Pin B is connected externally to the junction between resistors 16 and 18. Resistors 16 and 18 are coupled in series across VREF, at resistor 16, and −VOUT, at resistor 18. When the load increases, the absolute value of VOUT decreases, and thus the VC, output of error amplifier 40, increases. The conductive period of the switch 30 is controlled to vary in accordance with load current in the same manner as in the boost operation.
Another known method for boost conversion and inverting conversion implementation is illustrated in FIGS. 4A-4C. FIG. 4A depicts chip 10 with pins A and B illustrated. Pin A is connected internally to the negative input of error amplifier 40. The positive input of error amplifier 40 is connected internally to ground. The output of error amplifier 40 is connected to the negative input of error amplifier 41 through diode 43. Pin B is connected internally to the negative input of error amplifier 41. The positive input of error amplifier 41 is connected to VREF, which may be generated internally within chip 10. The output of error amplifier 41 produces voltage VC.
FIG. 4B illustrates the external connections to pins A and B for the arrangement shown in FIG. 4A for boost converter operation. Pin A is externally connected to the junction of resistors 16 and 18, which produces the feedback voltage VFB. Pins A and B are connected, externally, to each other. With this configuration, the feedback voltage VFB is applied to the negative input of error amplifier 41 with VREF applied at the positive input. VC is output to vary with load, as in the operation of FIG. 2, described above.
FIG. 4C illustrates the pin connections of the FIG. 4A arrangement for inverting operation. Pin A is externally connected to the junction of resistors 16 and 18, which produces the feedback voltage VFB. Pin B is connected externally to the other end of resistor 18. As VOUT has negative polarity in inverting operation, VFB is negative. Error amplifier 40 produces a positive output, which is applied via diode 43 to the negative input of error amplifier 41. The absolute value of feedback voltage VFB, increases for lighter load currents and decreases for heavier load currents. When the input to pin A becomes more negative (lighter load), the output of error amplifier 40, applied to the negative input of error amplifier 41, increases to decrease the output VC of error amplifier 41. Thus VC varies in correspondence with the increase and decrease of load current to obtain the same manner of regulation of switch 30 as in the operation of FIG. 2, described above.
The known arrangements require dedication of a plurality of IC pins to be externally reconfigured for operation as both boost and inverting conversion. The arrangement of FIGS. 3A-3C utilizes a single error amplifier, a permanent external connection of pin A to the reference voltage, and a reconfiguration of external connections to pins A through C when changing between boost and inverting converter operation. The arrangement of FIGS. 4A-4C utilizes two error amplifiers but still requires two pins for circuit reconfiguration when changing between boost and inverting converter operation. A need still exists for an integrated circuit switching regulator that needs no internal change for operation at either boost of inverting conversion while minimizing the number of pins needed to reconfigure operation.